1. Field of the Invention
The present invention relates to an evaluation facilitating circuit device for checking logical signal levels of each node of a logical circuit consisting of circuits, such as LSI circuits.
2 Description of the Prior Art
Conventionally, checking for simple logical circuits was carried out by use of a synchroscope or a tester, so as to detect logical signal levels at each node of the logical circuit, with a probe or probes being contacted to each node.
However, when a logical circuit becomes complex as a result of the fact that it is constructed of LSI integrated circuits, it can no longer be easily checked by the method described above.
In order to deal with this problem, ordinarily a check circuit is often incorporated in the logical circuit to be checked. Some techniques for overcoming the problem have heretofore been proposed; e.g. a circuit system for checking logical levels at each node of a logical circuit having latches to be used for a sequential circuit connected in series as in the case of LSSD, or pads provided on the LSI circuits to which a probe or stylus for checking the logical circuit is directly contacted. These techniques have, however, drawbacks in that these latches and pads are to be arranged irregularly in the LSI circuits.
Particularly, a recent predominating trend is that designs of the LSI circuits are being carried out by the use of automatic arrangement and wiring programs, when this approach is used, however, it becomes extremely difficult to provide for the latches and pads for which checks are required for identification on the LSI circuits, while the size of the integrated circuits becomes also large.
On the other hand, another method has also been proposed recently wherein internal nodes of a logical circuit are directly checked by the use of a EB tester. In this method as well, however, only relative potentials can be obtained and checking of logical circuits are not necessarily satisfactory.